As at current, we see that CMOS technology is the driving technology of the microelectronics industry, and the conventional way of fabricating integrated circuits on bulk silicon substrates has illustrated problems such as unwanted parasitic effects, latchup, and the difficulty of making shallow junctions. In the recent years, the advent of Silicon-on-Insulator has proven superior in many aspects to their bulk counterparts, and the benefits include the absence of latch-up, the reduced parasitic source and drain capacitances, the ease of making shallow junctions, radiation hardness, ability to operate at high temperature, improved transconductance and sharper subthreshold slope. There are several approaches available to create SOI wafers, and we discuss two particular techniques over here. First, we seek to illustrate a heteroepitaxy technique through the Ultra-Thin Silicon (UTSi) process where high quality Silicon-on-Sapphire (SOS) material is formed. Next, we look at a homoepitaxy technique called Epitaxial Lateral Overgrowth (ELO) technique which seeks to grow a homogenous crystal laterally on an insulator.
Ultra-Thin Silicon (UTSi) Process
Silicon-on-Sapphire (SOS) material was first introduced in 1964. SOS was recognized for its high speed and low power potential. The usage of Czochralski growth of sapphire crystals and the subsequent deposition of a silicon film in an epitaxial reactor had proved inefficient as there was high defect density due to lattice mismatch with defect densities near the Si-Sapphire interface reaching up to planar faults /cm and line defects/cm. This resulted in low resistivity, mobility, and lifetime near the interface. The silicon film deposited is also under compressive stress at room temperature due to different thermal expansion coefficients which may possibly result in relaxation in the film through crystallographic defects such as microtwins, stacking faults, and dislocations . Such consequences are undesired.
Hence, these reasons advocate the need for better heteroepitaxy technique, and in which the UTSi process is one such potential candidate. The steps involved in a UTSi process are as follows: See Figure 1.
Step 1: Grow a relatively thick film of silicon on sapphire. Silane (SiH4) is commonly used as the source of silicon for SOS growth. Its pyrolysis reaction in a carrier hydrogen gas, SiH4 –> Si + 2H2, results in the deposition of a silicon layer over the sapphire substrate. The deposition temperature is usually kept below 1050 deg C in order to prevent the autodeposition of aluminum from the sapphire substrate to the silicon layer. The desired silicon orientation is , which has been achieved on various sapphire orientations, i.e., , , .
Step 2: Implantation of Si into the silicon film is carried out to amorphize the bottom 2/3 of the silicon film, with the exception of a thin superficial layer, where the original defect density is the lowest.
Step 3: A low temperature thermal annealing step is then used to induce solid-phase regrowth of the amorphized silicon, using the top silicon layer as a seed.
Step 4: The silicon film is then thinned to the desired thickness by thermal oxidation, and the subsequent HF strip of the SiO. What remains is the final product of Silicon-on-Sapphire (SOS).
It has been demonstrated that UTSi process is capable of delivering relatively defect-free and stress free SOS material in which devices with a high effective mobility can be made.
One application of the UTSi process is seen in UTSi CMOS transistors. As seen from Figure 2, the fabrication process is much simpler since the deep implants and guard regions are unnecessary thanks to the insulating sapphire substrate, and undesired effects such as leakage currents, latchup, and the RF parasitics are eliminated since the devices now sit on an insulating layer. The performance of the CMOS process is enhanced by as much as two generations of process geometry reduction. The advantages of forming CMOS transistors in the ultra thin silicon layer over insulating sapphire include the following:
* Elimination of substrate capacitance, which allows higher speed at lower power and avoids voltage dependent capacitance distortions
* Fully depleted operation, improving linearity, speed, and low voltage performance
* Excellent isolation which allows integration of multiple RF functions without crosstalk
UTSi circuits are produced that compete in the rapidly expanding wireless and fiber optic markets at higher frequencies and data rates with lower power consumption than standard bulk CMOS, SiGe and GaAs circuits, while still using standard CMOS equipment and processing.
Epitaxial Lateral Overgrowth (ELO) Technique
This technique allows the homoepitaxial growth of silicon on silicon, with the focus placed on growing the crystal laterally on the insulator. In ELO, we can perform this in an atmospheric or in a reduced-pressure epitaxial reactor. The technique consists of the epitaxial growth of silicon from seeding windows over SiO islands or devices capped with an insulator.
The steps involved in a ELO technique are as follows: See Figure 3.
Step 1: An oxide layer is grown on the (100) silicon wafer. Next, patterning is carried out on the oxide to demarcate the windows. The edges of the windows are oriented along the direction.
Step 2: Cleaning of the wafer is carried out
Step 3: Wafer is loaded into an epitaxial reactor and submitted to a high-temperature hydrogen bake to remove the native oxide from the seeding windows.
Step 4: Epitaxial growth is performed next, using e.g: SiHCl +H+ HCL gas mixture.
Step 5: Apply an in-situ HCl etch step to remove any crystallites that may be formed on the oxide due to nucleation of small silicon crystals with random orientation during the epitaxial growth.
Step 6: Once the small nuclei are removed, a new epitaxial growth step is performed, followed by an etch step, and this repeats until the oxide is covered by epitaxial silicon.
Some points we should note is that the epitaxial growth proceeds from the seeding windows both vertically and laterally, and the silicon crystal is limited by the and facets. When two growth fronts, seeded from opposite sides of the oxide, join together, a continuous silicon-on-insulator film is formed, which contains a low-angle subgrain boundary where the two growth fronts meet. A groove is observed over the centre of the SOI area. When more growth is done, this groove disappears.
As much as this is a simple technique to have homoepitaxial growth, a major disadvantage is the nearly 1:1 lateral-to-vertical growth ratio. On the other hand, the thick ELO film allows the design engineer to obtain SOI films of different thickness easily simply by polishing the wafers to required depths as needed. Also, the low defect density and low thermal budget needed to implement a ELO-SOI is considered superior to other technologies such as SIMOX (Separation by Implanted Oxygen) or other SOI processes for submicron devices.
Applications for this technique have been seen in three-dimensional and double-gate devices.
Variations in ELO technique has been witnessed in “tunnel epitaxy”, “confined lateral selective epitaxy” (CLSEG) or “pattern-constrained epitaxy” (PACE) whereby a “tunnel” of SiO is created, forcing the epitaxial silicon to propagate laterally instead of vertically. In effect, a 7:1 lateral-to-vertical growth ratio has been obtained, which is more efficient than the original approach.
Jean-Pierre Colinge, Silicon-On-Insulator, Kluwer Academic Publishers, London, 2004.